module MFUNC_SUB1 ( /*AUTOARG*/
   // Outputs
   reg_MFUNC_SUB1_rd_data, params_other1, params_other2,
   params_other3, params_other4,
   // Inputs
   clk, rst_n, reg_MFUNC_SUB1_wr_en, sub_reg_addr, reg_wr_data,
   params_other5
   );
input         clk;
input         rst_n;
input         reg_MFUNC_SUB1_wr_en;
input  [ 7:0] sub_reg_addr;
input  [ 7:0] reg_wr_data;
output [ 7:0] reg_MFUNC_SUB1_rd_data;
output           params_other1;
output  [7:0]   params_other2;
output  [7:0]   params_other3;
output  [7:0]   params_other4;
input            params_other5;
/////////////////////////////////////////////////////
reg  [ 7:0]   reg_MFUNC_SUB1_rd_data;
reg           reg_00;
reg  [7:0]   reg_01;
reg  [7:0]   reg_02;
reg  [7:0]   reg_03;
reg           reg_04;
wire          wr_00_en;
wire          wr_01_en;
wire          wr_02_en;
wire          wr_03_en;
wire          wr_04_en;
assign          wr_00_en=(reg_MFUNC_SUB1_wr_en&&(sub_reg_addr==8'h00));
assign          wr_01_en=(reg_MFUNC_SUB1_wr_en&&(sub_reg_addr==8'h01));
assign          wr_02_en=(reg_MFUNC_SUB1_wr_en&&(sub_reg_addr==8'h02));
assign          wr_03_en=(reg_MFUNC_SUB1_wr_en&&(sub_reg_addr==8'h03));
assign          wr_04_en=(reg_MFUNC_SUB1_wr_en&&(sub_reg_addr==8'h04));
/////////////////////////////////////////////////////
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_00<=1'd0;
    end
    else if (wr_00_en) begin
       reg_00<=reg_wr_data;
    end
end
assign  params_other1=reg_00;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_01<=8'h03;
    end
    else if (wr_01_en) begin
       reg_01<=reg_wr_data;
    end
end
assign  params_other2=reg_01;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_02<=8'h02;
    end
    else if (wr_02_en) begin
       reg_02<=reg_wr_data;
    end
end
assign  params_other3=reg_02;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_03<=8'h01;
    end
    else if (wr_03_en) begin
       reg_03<=reg_wr_data;
    end
end
assign  params_other4=reg_03;
always @(posedge clk or negedge rst_n)
begin
    if (~rst_n) begin
       reg_04<=1'd0;
    end
    else  begin
       reg_04<=params_other5;
    end
end
always @( * )
begin
    case(sub_reg_addr) 
    8'h00 : reg_MFUNC_SUB1_rd_data=reg_00;
    8'h01 : reg_MFUNC_SUB1_rd_data=reg_01;
    8'h02 : reg_MFUNC_SUB1_rd_data=reg_02;
    8'h03 : reg_MFUNC_SUB1_rd_data=reg_03;
    8'h04 : reg_MFUNC_SUB1_rd_data=reg_04;
    default : reg_MFUNC_SUB1_rd_data=8'h5a;
    endcase
end
endmodule
